19th IEEE International Symposium on
April 20-22, 2016, Košice, Slovakia
University of Bologna, Italy
The main challenges posed today’s by the continuous advances of microelectronic technology will be addressed. Particularly, the test and reliability challenges posed by emerging new kind of faults and their possible interaction will be discussed, as well as possible design solutions to avoid their dramatic impact on system’s reliability.
Cecilia Metra is a Full Professor in Electronics at the University of Bologna, Italy, where she received the Ph.D. in Electronic Engineering and Computer Science in 1995. In 2002, she was a Visiting Faculty Consultant for Intel Corporation in the USA.
She is Member of the Board of Governors of the IEEE Computer Society for 2013-2015, and she has been re-elected Member of the Board of Governors for 2016-2018 (resulting the mostly voted, with 4.249 votes). She has also been Vice-President for Technical and Conference Activities of the IEEE Computer Society for 2014, and member of the IEEE Computer Society Executive Committee for 2014-2015.
She is the Editor-in-Chief of the on-line magazine Computing Now, a member of the Advisory or Editorial Board of several other professional Journals, and she was the Associate Editor-in-Chief of IEEE Transactions on Computers (2007–2012). She has been involved in numerous IEEE sponsored Symposia/Workshops as General/Program Chair/Co-Chair, and as Technical Program Committee Member.
Her research interests are in the field of Design and Test of Digital Systems, Reliable and Error Resilient Systems’ Design, Fault Tolerance, On-Line Testing, Fault Modeling, Diagnosis and Debug, Emergent Technologies and Nano Computing, Secure Systems, Energy Harvesting Systems, Photovoltaic Systems. She extensively published in these fields.
She is an IEEE Fellow Member and a Golden Core Member of the IEEE CS, and she received two Meritorious Service Awards and three Certificates of Appreciation from the IEEE CS.
University of Grenoble, France
Assertion-based design is a set of methods and tools to support the unambiguous specification of what behavior a system should display, and ensure the consistency between its design and its specification. Initially developed at the register transfer level (RTL), specialized languages such as PSL or SVA have been extended to apply to the more abstract transaction level, thus raising the issue of propagating requirement and properties across design levels. Assertions can be fed to a simulator or a model checker, for direct use in simulation or formal verification.
Another approach, that enables property reuse also in emulation, is the compilation of assertions into verification IP's that are connected to the design. These are usually understood to be observers that are connected to the design and check if the properties are violated: this is what the CAD industry provides as assertion synthesis result.
A newer and long-term perspective is the direct production of compliant hardware modules from a set of assertions, either at gate level, or as a synthesizable RTL design. This fast prototyping from assertions has not yet reached maturity, but may already be used to replace a missing module, and provide valuable support for assertions debugging.
The talk will present the various facets of assertion-based design, and will review the results obtained, and the on going works, after ten years of research at TIMA Laboratory.
Dominique Borrione received the M.S., PhD and Thèse d'Etat degrees in Computer Science from the University of Grenoble, France, in 1972, 1976 and 1981. She has been Professor with the Univ. of Marseille (1983-1988), then with the Engineering Department of Grenoble University (1988-2015). Since September 2015, she is Professor Emeritus of the University of Grenoble. She served as Director of the TIMA Laboratory from 2007 to 2014. She has worked on various aspects of hardware design automation: design languages, simulation, formal verification, synthesis, multi-level design tools. Her current interests cover design specifications and the use of formal methods supporting the various tools along the design flow. She received the distinguished IFIP Silver Core.
Manager of the Competence Center Embedded Systems Design Automation
OFFIS Research Institute in Oldenburg, Germany
Safety critical devices such as automotive embedded systems use technology nodes, several years behind the state of the art – as defined by processors or memories. For these cutting edge devices, recently occurring degradation effects such as Bias Temperature Instability (BTI) and Hot Carrier Degradation (HCD) are already a major challenge. But as soon as safety critical devices approach the current technology nodes, the combination of their safety requirements and massive degradation from recent nodes will result in a severe reliability issue.
For all safety critical devices, controlling reliability will lead to enormous overdesign, not only at the circuit level, but already at the early levels of abstraction where various adaptation and redundancy schemes are available. This overdesign will of course reduce the benefit of technology scaling. In the moment, where the overhead for controlling a new node’s reliability exceeds its scaling benefits, Moore’s law will stop – at least for a given reliability level.
In order to enjoy the scaling benefits for as long as possible, especially for high reliability devices, an efficient way of ensuring reliability is required. In order to trade off reliability enhancement techniques versus their drawbacks and overheads, an assessment methodology as early as possible in the design flow is desirable.
Domenik Helms studied Quantum Mechanics till 2001 and received his PhD on Leakage Models for High Level Power Estimation in 2009. Currently he is the manager of the Competence Center Embedded Systems Design Automation at the OFFIS research institute in Oldenburg, Northern Germany. Domenik’s current research interest is the early (in the design) prediction of extra-functional properties such as timing, power, temperature, variation and ageing.